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njw4152- a b - 1 - ver.2013-01-23 switching regulator ic for buck converter w/ 40v/1a mosfet general description package outline features maximum rating input voltage 45v wide operating voltage range 3.6v to 40v @ab version switching current 1.4a(min.) @ab version pwm control wide oscillating frequency 300khz to 1mhz soft start function 4ms typ. uvlo (under voltage lockout) over current protection / thermal shutdown protection standby function package outline njw4152gm1: hsop8 product classification status part number version output current switching current limit (min.) operating voltage package operating temperature range mp njw4152gm1-a a 1.0a 1.4a 4.6 to 40v hsop8 general spec. -40 to +85 c mp njw4152gm1-a-t a 1.0a 1.4a 4.6 to 40v hsop8 automotive t spec. -40 to +105 c mp NJW4152GM1-A-T1 a 1.0a 1.4a 4.6 to 40v hsop8 automotive t1 spec. -40 to +125 c mp njw4152gm1-ab ab 1.0a 1.4a 3.6 to 40v hsop8 general spec. -40 to +85 c mp njw4152gm1-ab-t1 ab 1.0a 1.4a 3.6 to 40v hsop8 automotive t1 spec. -40 to +125 c mp njw4152r-b b 600ma 0.8a 4.6 to 40v msop8 (vsp8) general spec. -40 to +85 c u.d. njw4152r-ba-z ba 600ma 0.8a 4.4 to 40v msop8 (vsp8) automotive z spec. -40 to +125 c this data sheet is applied to "njw4152gm1-ab". please refer to each data sheet for other versions. the njw4152 is a buck converter with 40v/1a mosfet. it corresponds to high oscillating frequency, and low esr output capacitor (mlcc) within wide input range from 3.6v to 40v. therefore, the njw4152 can realize downsizing of an application with a few external parts. also, it has a soft start function, an over current protection and a thermal shutdown circuit. moreover there is an automotive for extended operating temperature range version. it is suitable for logic voltage generation from high voltage that car a ccessor y , office automation equipment, industrial instrument and so on. njw4152gm1-ab
njw4152-ab - 2 - ver.2013-01-23 pin configuration njw4152gm1-ab block diagram buffer soft start 0.8v in- pwm er ? amp gnd tsd standby on/off on/off high: on low : off (standby) uvlo sw vref osc fb rt pv + v + regulator ocp pulse by pulse 480k ? low frequency control pin function 1. pv + 2. v + 3. on/off 4. rt 5. in- 6. fb 7. gnd 8. sw 1 4 3 2 8 5 6 7 exposed pad on backside connect to gnd
njw4152- a b - 3 - ver.2013-01-23 absolute maximum ratings (ta=25c) parameter symbol maximum ratings unit supply voltage (v + pin, pv + pin) v + +45 v pv + - sw pin voltage v pv-sw +45 v in- pin voltage v in- -0.3 to +6 v on/off pin voltage v on/off +45 v power dissipation p d hsop8 790 (*1) 2,500 (*2) mw junction temperature range tj -40 to +150 c operating temperature range t opr -40 to +85 c storage temperature range t stg -40 to +150 c (*1): mounted on glass epoxy board. (76.2 114.3 1.6mm:eia/jdec standard size, 2layers) (*2): mounted on glass epoxy board. (76.2 114.3 1.6mm:eia/jdec standard size, 4layers), internal cu area: 74.2 74.2mm recommended operating conditions parameter symbol min. typ. max. unit supply voltage v + 3.6 ? 40 v output current (*3) i out ? ? 1.0 a timing resistor r t 18 27 68 k ? oscillating frequency fosc 300 700 1,000 khz (*3): at static status
njw4152-ab - 4 - ver.2013-01-23 electrical characteristics (unless otherwise noted, v + =v on/off =12v, r t =27k ? , ta=25 c) parameter symbol test condition min. typ. max. unit under voltage lockout block on threshold voltage v t_on v + = l h 3.2 3.4 3.6 v off threshold voltage v t_off v + = h l 3.1 3.3 3.5 v hysteresis voltage v hys 60 100 ? mv soft start block soft start time t ss v b =0.75v 2 4 8 ms oscillator block oscillation frequency f osc 630 700 770 khz oscillation frequency (low frequency control) f osc_low v in- =0.4v, v fb =0.55v ? 270 ? khz rt pin voltage v rt 0.24 0.275 0.31 v oscillation frequency deviation (supply voltage) f dv v + =4.6v to 40v ? 1 ? % oscillation frequency deviation (temperature) f dt ta = - 4 0 c to +85 c ? 2 ? % error amplifier block reference voltage v b -1.0% 0.8 +1.0% v input bias current i b -0.1 ? +0.1 a open loop gain a v ? 80 ? db gain bandwidth g b ? 0.6 ? mhz output source current i om+ v fb =1v, v in- =0.7v 8 16 24 a output sink current i om- v fb =1v, v in- =0.9v 1 2 4 ma pwm comparate block maximum duty cycle m ax d uty v in- =0.7v 100 ? ? % output block output on resistance r on i sw =1a ? 0.3 0.5 ? switching current limit i lim 1.4 1.7 2.0 a switching leak current i leak v on/off =0v, v + =45v, v sw =0v ? ? 1 a on/off block on control voltage v on v on/off = l h 1.6 ? v + v off control voltage v off v on/off = h l 0 ? 0.5 v pull-down resistance r pd ? 480 ? k ? general characteristics quiescent current i dd r l =no load, v in- =0.7v, v fb =0.55v ? 2.5 2.8 ma standby current i dd_stb v on/off =0v ? ? 1 a
njw4152- a b - 5 - ver.2013-01-23 typical applications c nf r nf sw 8 7 6 5 1 2 3 4 fb gnd in- rt v + c fb r2 c out l sbd njw4152 v in c in1 r1 v out r fb r t pv + on/off on/off high: on low: off (standby) c in2
njw4152-ab - 6 - ver.2013-01-23 characteristics oscillation frequency vs. supply voltage (r t =27k ? , ta=25c) 630 650 670 690 710 730 750 770 0 10203040 supply voltage v + (v) oscillation frequnecny f osc (khz) output on resistance vs. supply voltage (ab ver., ta=25c) 0.20 0.22 0.24 0.26 0.28 0.30 0.32 0.34 0.36 0.38 0.40 0 10203040 supply voltage v + (v) output on resistance r on ( ? ) reference voltage vs. supply voltage (ab ver., ta=25c) 0.79 0.795 0.8 0.805 0.81 0 10203040 supply voltage v + (v) reference voltage v b (v) quiescent current vs. supply voltage (r t =27k ? , r l =no load, v in- =0.7v, ta=25c) 0 1 2 3 4 0 10203040 supply voltage v + (v) quiescent current i dd (ma) error amplifier block voltage gain, phase vs. frequency (v + =12v, gain=40db, ta=25c) 0 15 30 45 60 10 100 1k 10k 100k 1m 10m frequency f (hz) voltage gain av (db) 0 45 90 135 180 phase (deg) gain phase timing resistor vs. oscillation frequency (v + =12v, ta=25c) 100 1000 10 100 timing resistor r t (k ? ) oscillation frequnecny f osc (khz)
njw4152- a b - 7 - ver.2013-01-23 characteristics oscillation frequency vs temperature (v + =12v, r t =27k ? ) 660 680 700 720 740 -50 -25 0 25 50 75 100 125 150 ambient temperature ta (c) oscillation frequency fosc (khz) reference voltage vs. temperature (v + =12v) 0.792 0.794 0.796 0.798 0.800 0.802 0.804 0.806 0.808 -50 -25 0 25 50 75 100 125 150 ambient temperature ta (c) reference voltage v b (v) limited switching current vs. temperature (ab ver.) 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 -50 -25 0 25 50 75 100 125 150 ambient temperature ta (c) limited switching current i lim (a) v + =40v v + =12v v + =3.6v output on resistance vs. temperature (ab ver., i sw =1a) 0 0.1 0.2 0.3 0.4 0.5 0.6 -50 -25 0 25 50 75 100 125 150 ambient temperature ta (c) output on resistance r on ( ? ) v + =3.6v v + =4v v + =6v v + =12v, 40v under voltage lockout voltage vs. temperature (ab ver.) 3.1 3.2 3.3 3.4 3.5 3.6 -50 -25 0 25 50 75 100 125 150 ambient temperature ta (c) threshold voltage (v) v t_on v t_off soft start time vs. temperature (v + =12v, v b =0.75v) 2 3 4 5 6 7 8 -50-25 0 255075100125150 ambient temperature ta (c) soft start time tss (ms)
njw4152-ab - 8 - ver.2013-01-23 characteristics quiescent current vs. temperature (r t =27k ? , r l =no load, v in- =0.7v) 0 0.5 1 1.5 2 2.5 3 3.5 4 -50 -25 0 25 50 75 100 125 150 ambient temperature ta (c) quiescent current i dd (ma) v + =12v v + =40v v + =3.6v standby current vs. temperature (v on/ff =0v) 0 0.2 0.4 0.6 0.8 1 -50 -25 0 25 50 75 100 125 150 ambient temperature ta (c) standby current i dd_stb (a) v + =12v v + =40v switching leak current vs. temperature (v + =45v, v on/off =0v, v sw =0v) 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 150 ambient temperature ta (c) switching leak current i leak (a)
njw4152- a b - 9 - ver.2013-01-23 pin descriptions pin number pin name function 1 pv + power supply pin for power line 2 v + power supply pin for ic control 3 on/off on/off control pin the on/off pin internally pulls down with 480k ? . normal operation at the time of high level. standby mode at t he time of low level or open. 4 rt oscillating frequency setting pin by timing resistor. oscillating frequency should set between 300khz and 1mhz. 5 in- output voltage detecting pin connects output voltage through the resistor divider tap to this pin in order to voltage of the in- pin become 0.8v. 6 fb feedback setting pin the feedback resistor and capacitor are connected between the fb pin and the in- pin. 7 gnd gnd pin 8 sw switch output pin of power mosfet ? exposed pad connect to gnd description of block features 1. basic functions / features error amplifier section (er ? amp) 0.8v1% precise reference voltage is connecte d to the non-inverted input of this section. to set the output voltage, connects converter's output to inve rted input of this section (in- pin). if requires output voltage over 0.8v, inserts resistor divider. because the reference voltage has decreased supply vo ltage on the operating conditions less than 4v*, please confirm "reference voltage vs. s upply voltage" characteristic. this amp section has high gain and ex ternal feedback pin (fb pin). it is easy to insert a feedback resistor and a capacitor between the fb pin and the in- pin, making possi ble to set optimum loop compensation for each type of application. (* design value) oscillation circuit section (osc) oscillation frequency can be set by inserting resistor between the rt pin and gnd. referring to the sample characteristics in "timing resistor and oscillation frequency", set oscillation between 300khz and 1mhz. technical information njw 41 5 2 - a b application manual
njw4152-ab - 10 - ver.2013-01-23 description of block features (continued) pwm comparator section (pwm) this section controls th e switching duty ratio. pwm comparator receives the signal of the error amplif ier and the triangular wave, and controls the duty ratio between 0% and 100%. the timing chart is shown in fig.1. sw pin fb pin voltage on off osc wavef orm (ic internal) maximum duty: 100% fig. 1. timing chart pwm comparator and sw pin power mosfet (sw output section) the power is stored in the inductor by the switch operati on of built-in power mosfet. the output current is limited to 1.4a(min.)@ab version by the overcurrent protection function. in case of step-down converter, the forward direction bias voltage is generated with inductance current that flows into the external regenerative diode when mosfet is turned off. the sw pin allows voltage between the pv + pin and the sw pin up to +45v. however, you should use an schottky diode that has low saturation voltage. when the power supply voltage decreases, on resistan ce rises. because a dropout voltage in the mosfet becomes large if an output current is large, please be ca reful about input-output differential voltage of the application. power supply, gnd pin (v + , pv + and gnd) in line with switching element drive, current flows in to the ic according to frequency. if the power supply impedance provided to the power supply circuit is high, it will not be possible to take advantage of ic performance due to input voltage fluctuation. therefore insert a bypass capacitor close to the v + pin ? the gnd pin connection in order to lower high frequency impedance. technical information njw 41 5 2 -ab application manual
njw4152- a b - 11 - ver.2013-01-23 2. additional and protection functions / features under voltage lockout (uvlo) the uvlo circuit operating is released above v + =3.4v(typ.) and ic operation starts. when power supply voltage is low, ic does not operate because the uvlo circuit oper ates. there is 100mv width hysteresis voltage at rise and decay of power supply voltage. hysteresis prevents the malfunction at the time of uvlo operating and releasing. soft start function (soft start) the output voltage of the converter gradually rises to a set value by the soft start function. the soft start time is 4ms (typ). it is defined with the time of the error amplifie r reference voltage becoming from 0v to 0.75v. the soft start circuit operates after the release uvlo and/or recovery from thermal shutdown. the operating frequency is controlled with a low frequency, approximately 40% of the set va lue by the timing resistor, until voltage of the in- pin becomes approximately 0.4v. sw pin 0.8v fb pin voltage on off vref, in- pin voltage osc wavef orm steady operaton uvlo(3.4v typ.) release, standby, recover from thermal shutdow n soft start effective period to v b =0.8v soft start time: tss=4ms(typ.) to v b =0.75v low frequency control v in- =approx 0.4v fig. 2. startup timing chart technical information njw 41 5 2 - a b application manual
njw4152-ab - 12 - ver.2013-01-23 description of block features (continued) over current protection circuit (ocp) at when the switching current becomes i lim or more, the overcurrent protection circuit is stopped the mosfet output. the switching output holds low level down to next pulse output at ocp operating. the njw4152 output returns automatically along with re lease from the over current condition because the ocp is pulse-by-pulse type. fig.3. shows the timing chart of th e over current protection detection. if voltage of the in- pin becomes less than 0.4v, the oscillation frequency decreases to approximately 40% and the energy consumption is suppressed. sw pin fb pin voltage on off osc wavef orm sw itching current i lim 0 static status detec t overcurrent static status fig. 3. timing chart at over current detection thermal shutdown function (tsd) when junction temperature of the njw4152 exceeds the 175c*, internal thermal shutdown circuit function stops sw function. when junction temperature decreases to 145c* or less, sw operation returns with soft start operation. the purpose of this function is to prevent malfunctioning of ic at the high junction temperature. therefore it is not something that urges positive use. you should make sure to operate within the junction temperature range rated (150 c). (* design value) on/off function (standby control) the njw4152 stops the operating and becomes standby stat us when the on/off pin becomes less than 0.5v. the on/off pin internally pulls down with 480k ? , therefore the njw4152 becomes standby mode when the on/off pin is open. you should connect this pin to v + when you do not use on/off function. technical information njw 41 5 2 -ab application manual
njw4152- a b - 13 - ver.2013-01-23 application information inductors large currents flow into inductor, therefore you must provide current capacity that does not saturate. reducing l, the size of the inductor can be smaller. however, peak current increases and adversely affecting efficiency. on the other hand, increasing l, peak current can be reduced at switching time. therefore conversion efficiency improves, and output ripple voltage reduces. above a certain level, increasing inductance windings increases loss (copper loss) due to the resistor element. ideally, the value of l is set so that inductance current is in continuous conduction mode. however, as the load current decreases, the current waveform changes from (1) ccm: continuous conduction mode (2) critical mode (3) dcm: discontinuous conduction mode (fig. 4.). in discontinuous mode, peak current increases with respec t to output current, and conversion efficiency tend to decrease. depending on the situation, increase l to widen the load current area to maintain continuous mode. if the application needs maximum output current, the indu ctor ripple current should be set less than 20% to prevent operating the over current protection circ uit at the minimum switching limiting current. catch diode when the switch element is in off cycle, power stored in the inductor flows via the catch diode to the output capacitor. therefore during each cycle current flows to the diode in response to load current. because diode's forward saturation voltage and current accumulation caus e power loss, a schottky barrier diode (sbd), which has a low forward saturation voltage, is ideal. an sbd also has a short reverse recovery time. if the reve rse recovery time is long, through current flows when the switching transistor transitions from off cycle to on cycle. this current may lower efficiency and affect such factors as noise generation. input capacitor transient current flows into the input section of a swit ching regulator responsive to frequency. if the power supply impedance provided to the power supply circuit is large, it will not be possible to take advantage of the njw4152 performance due to input voltage fluctuation. therefore in sert an input capacitor as close to the mosfet as possible. output capacitor an output capacitor stores power from the induc tor, and stabilizes voltage provided to the output. when selecting an output capacitor, you must consider equi valent series resistance (esr ) characteristics, ripple current, and breakdown voltage. also, the ambient temperature affects capacitors, decreasing capacitance and increasing esr (at low temperature), and decreasing lifetime (at high temperature) . concerning capacitor rating, it is advisable to allow sufficient margin. output capacitor esr characteristics have a major influe nce on output ripple noise. a capacitor with low esr can further reduce ripple voltage. be sure to note the follo wing points; when ceramic capacit or is used, the capacitance value decreases with dc voltage applied to the capacitor. 0 inductor current ? i l t off t on peak current ipk frequency f osc current (1) continuous conduction mode (2) critical mode (3) continuous conduction mode fig. 4. inductor current state transition technical information njw 41 5 2 - a b application manual
njw4152-ab - 14 - ver.2013-01-23 application information (continued) board layout in the switching regulator application, because the cu rrent flow corresponds to the oscillation frequency, the substrate (pcb) layout becomes an important. you should attempt the transition voltage decrease by maki ng a current loop area minimize as much as possible. therefore, you should make a current flowing line thick and short as much as possible. fig.5. shows a current loop at step-down converter. especially, should lay out high priority the loop of c in -sw-sbd that occurs rapid current change in the switching. it is effective in reduci ng noise spikes caused by parasitic inductance. njw4152 built-in sw c out l sbd c in v in njw4152 built-in sw c out l sbd c in v in (a) buck converter sw on (b) buck converter sw off fig. 5. current loop at buck converter concerning the gnd line, it is preferred to separate the power system and the signal system, and use single ground point. the voltage sensing feedback li ne should be as far away as possible from the inductance. because this line has high impedance, it is laid out to avoid the influence noise caused by flux leaked from the inductance. fig. 6. shows example of wiring at buck conver ter. fig. 7 shows the pcb layout example. to avoid the influence of the voltage drop, the output voltage should be detected near the load. sw gnd in- rt v + c fb r2 c out l sbd njw4152 c in r1 v out r fb r t pv + v in r l because in- pin is high impedance, the voltage detection resistance: r1/r2 is put as much as possible near ic(in-). separate digital(signal) gnd f rom pow er gnd (bypass capacitor) fig. 6. board layout at buck converter technical information njw 41 5 2 -ab application manual
njw4152- a b - 15 - ver.2013-01-23 application information (continued) r1 r2 c fb c out l sbd c in1 r fb r t c nf r nf c in2 on/off v in v out feed back signal signal gnd area power gnd area to signal gnd gnd in gnd out connect signal gnd line and power gnd line on backside pattern fig. 7 layout example (upper view) technical information njw 41 5 2 - a b application manual
njw4152-ab - 16 - ver.2013-01-23 calculation of package power a lot of the power consumption of buck converter occurs from the internal switching element (power mosfet). power consumption of njw4152 is roughly estimated as follows. input power: p in = v in i in [w] output power: p out = v out i out [w] diode loss: p diode = v f i l(avg) off duty [w] njw4152 power consumption: p loss = p in ? p out ? p diode [w] where: v in : input voltage for converter i in : input current for converter v out : output voltage of converter i out : output current of converter v f : diode's forward saturation voltage i l(avg) : inductor average current off duty : switch off duty efficiency ( ) is calculated as follows. = (p out p in ) 100 [%] you should consider temperature derating to the calculated power consumption: p d . you should design power consumption in rated range refe rring to the power dissipation vs. ambient temperature characteristics (fig. 8). njw4152gm1-ab (hsop8 package) power dissipation vs. ambient temperature (tj=~150c) 0 500 1000 1500 2000 2500 3000 -50 -25 0 25 50 75 100 125 150 ambient temperature ta (c) power dissipation p d (mw) at on 2 layer pc board at on 4 layer pc board general spec extended t1 spec mounted on glass epoxy board. (76.2 114.3 1.6mm:eia/jdec standard size, 2layers) mounted on glass epoxy board. (76.2 114.3 1.6mm:eia/jdec standard size, 4layers), internal cu area: 74.2 74.2mm fig. 8. power dissipation vs. am bient temperature characteristics technical information njw 41 5 2 -ab application manual
njw4152- a b - 17 - ver.2013-01-23 application design examples step-down application circuit ic input voltage : njw4152gm1 : v in =12v output voltage : v out =5v output current : i out =1a oscillation frequency : fosc=700khz output ripple voltage : v ripple(p-p) =less than 20mv c nf 4,700pf r nf 3.3k ? sw 8 7 6 5 1 2 3 4 fb gnd in- rt v + c fb 220pf r2 27k ? c out 4.7 f/6.3v l 22 h/2.5a sbd njw4152gm1 v in =12v c in1 10 f/50v r1 5.1k ? v out =5v r fb 0 ? ? pv + on/off onoff high: on low: off (standby) c1 open c in2 0.1 f/50v reference qty. part number description manufacturer ic 1 njw4152gm1 internal 1a mosfet sw.reg. ic new jrc l 1 cdrh8d28hpnp-220n inductor 22 h, 2.5a(ta=20 c) / 1.9a (ta=100 c) sumida d 1 cms11 schottky diode 40v, 2a toshiba c in1 1 umk325bj106mm ceramic capacitor 3225 10 f, 50v, x5r taiyo yuden c in2 1 0.1 f ceramic capacitor 1608 0.1 f, 5 0 v, b std. c out 1 jmk212abj475kg ceramic capacitor 2012 4.7 f, 6 . 3 v, x 5 r taiyo yuden c nf 1 4,700pf ceramic capacitor 1608 4,700pf, 50v, b std. c fb 1 220pf ceramic capacitor 1608 220pf, 50v, ch std. c1 0 ? (optional) optional ? r1 1 5.1k ? resistor 1608 5.1k ? , 1%, 0.1w std. r2, r t 2 27k ? resistor 1608 27k ? , 1%, 0.1w std. r nf 1 3.3k ? resistor 1608 3.3k ? , 5%, 0.1w std. r fb 1 0 ? (short) resistor 1608 0 ? , 0.1w std. technical information njw 41 5 2 - a b application manual
njw4152-ab - 18 - ver.2013-01-23 application design examples (continued) setting oscillation frequency from the oscillation frequency vs. timing resistor characteristic, r t =27 [k ? ], t=1.43[ s] at fosc=700khz. step-down converter duty ratio is shown with the following equation. [] % 45 100 12 4 . 0 5 100 = + = + = in f out v v v duty therefore, t on =0.64 [ s], t off =0.79 [ s] fig. 9. inductor current waveform selecting inductance to assume maximum output current: 1a, and the inductor ri pple current should be set not to exceed the minimum switching limiting current: i lim =1.4a (min.). ? il is inductance ripple current. when to ? il= output current 20%: ? i l = 0.2 i out = 0.2 1 = 0.2 [a] this obtains inductance l. v ds_ron is drop voltage by mosfet on resistance. on l out ron ds in t i v v v l ? ? ? = ? ] [ 8 . 20 64 . 0 2 . 0 5 5 . 0 12 h = ? ? = ? 22[ h] inductance l is a theoretical value. the optimum value vari es according such factors as application specifications and components. fine-tuning should be done on the actual device. this obtains the peak current ipk at switching time. ] [ 1 . 1 2 2 . 0 1 2 a i i ipk l out = + = ? + = the current that flows into the inductance provides sufficient margin for peak current at switching time. in the application circuit, use l=22 h, 2.5a(ta=20 c) / 1.9a (ta=100 c). 0 t off t on period: t frequency: f osc =1/t inductance current: ? i l output current: i out peak current: ipk technical information njw 41 5 2 -ab application manual
njw4152- a b - 19 - ver.2013-01-23 application design examples (continued) selecting the input capacitor the input capacitor corresponds to the input of the pow er supply. it is requir ed to adequately reduce the impedance of the power supply. the input capacitor select ion should be determined by the input ripple current and the maximum input voltage of the capaci tor rather than its capacitance value. the effective input current can be expressed by the following formula. () ] [ a v v v v i i in out in out out rms ? = in the above formula, the maximum current is obtained when v in = 2 v out , and the result in this case is i rms = i out (max) 2. when selecting the input capacitor, carry out an evaluati on based on the application, and use a capacitor that has adequate margin. selecting the output capacitor the output capacitor is an important component that determi nes output ripple noise. equivalent series resistance (esr), ripple current, and capacitor breakdown voltage are important in determining the output capacitor. the output ripple noise can be expr essed by the following formula. l p p ripple i v esr ? = ? ) ( when selecting output capacitance, select a capaci tor that allows for sufficient ripple current. the effective ripple current that flows in a capacitor (i rms ) is obtained by the following equation. ] [ 58 3 2 2 . 0 3 2 marms i i l rms = = ? = consider sufficient margin, and use a ca pacitor that fulfills the above spec. in the application circuit, use c out =4.7 f/6.3v. setting output voltage the output voltage v out is determined by the relative resistances of r1, r2. the current that flows in r1, r2 must be a value that can ignore the bias current that flows in er amp. ] [ 04 . 5 8 . 0 1 1 . 5 27 1 1 2 v k k v r r v b out = ? ? ? ? ? ? + = ? ? ? ? ? ? + = technical information njw 41 5 2 - a b application manual
njw4152-ab - 20 - ver.2013-01-23 compensation design example a switching regulator requires a f eedback circuit for acquiring a stable output. because the frequency charac teristics of the application change according to the inductance, output capacitor, and so on, the compensation constant should ideally be determined in such a way that the maximum band is acquired while the necessary phase for stable operation is maintained. these compensation constants play an important role in the adjustment of the njw4152 when mounted in an actual unit. finally, select the constants while performing measurement, in consideration of the application specifications. feedback and stability basically, the feedback loop should be designed in such a way that the open loop phase shift at the point where the loop gain is 0 db is less than -180 . it is also important that the loop characteristics have margin in consideration of ringing and immunity to oscillation during load fluctuations. with the njw4152, the feedback circuit can be freely designed, enabling the arrangement of the poles and zeros whic h is important for loop compensation, to be optimized. the characteristics of the poles and zeros are shown in fig. 10. poles: the gain has a slope of -20 db/dec, and the phase shifts -90 . zeros: the gain has a slope of +20 db/dec, and the phase shift +90 . if the number of factors constituting poles is defined as ?n ?, the change in the gain and phase will be ?n?-fold. this also applies to zeros as well. the poles and zeros are in a re ciprocal relationship, so if there is one factor for each pole and zero, they will cancel each other. configuration of the compensation circuit v out c fb c1(option) r esr c out l buffer v in pwm lc gain c nf r nf vref =0.8v in- fb er ? amp r2 r1 c fb r fb sw pv + fig. 11. compensation circuit configuration fig. 10. characteristics of pole and zero gain phase -20db/dec f p /10 10f p f p -45 0 -90 frequency gain phase +20db/dec f z /10 10f z f z +45 0 +90 frequency pole zero pole zero technical information njw 41 5 2 -ab application manual
njw4152- a b - 21 - ver.2013-01-23 compensation design (continued) poles and zeros due to the inductance and output capacitor double poles f p(lc) are generated by the inductance and output capacitor. simultaneously, single zeros f z(esr) are generated by the output capacitor and esr. each pole and zero is expressed by the following formula. esr out ) esr ( z r c 2 1 f = out ) lc ( p lc 2 1 f = if the esr of the output capacitor is high, f z(esr) will be located in the vicinity of f p(lc) . in an application such as this, the zero f z(esr) compensates the double poles f p(lc) , resulting in a tendency for stability to be readily maintained. however, if the esr of the output capacitor is low, f z(esr) shifts to the high region, and the phase is shifted -180 by f p(lc) .the njw4152 compensation circuit enables compens ation to be realized by using zeros f z1 and f z2 . poles and zeros due to error amplifier the single poles and zeros generated by the error amplifier are obtained using the following formula. zero pole nf nf 1 z r c 2 1 f = ? ? ? ? ? ? + = 2 r 1 r 2 r 1 r a c 2 1 f v nf 1 p (av: amplifier open loop gain=80db) 2 r c 2 1 f fb 2 z = ? ? ? ? ? ? + + = 2 r 1 r 2 r 1 r r c 2 1 f fb fb 2 p nf 3 p r 1 c 2 1 f = (option) f z1 and f z2 are located on both sides of f p(lc) . because the inductance and output capacitor vary, they are each set using the following as a rough guide. f p(lc) 0.5-fold ? 0.9-fold f p(lc) 1.1-fold ? 2.0-fold there is also a method in which f z1 and f z2 are located at positions lower than even f p(lc) . because there is a tendency for the phase shift to increase and the gain to rise , it can be expected that the response will improve. however, there is a tendency for the phase margin to become insufficient, so care is necessary. f p1 creates poles in the low frequency region due to the miller effect of the error amplifier. the stability becomes better as f p1 becomes lower. on the other hand, the frequency char acteristics do not improve, so the response is adversely affected. f p1 is set using a frequency gain of 20 db for f p(lc) as a rough guide. if the open loop gain of the error amplifier is made 80 db, design is carried out using f p1 < f p(lc) 10 3 (= 60 db) as a rough guide. above several 100 khz, various poles are generated, so the upper limit of the frequency range where the loop gain is 0 db is set to fifth (1/5) to tenth (1/10) of oscillation frequency. the f z(esr) in the high frequency region sometimes causes a loop gain to be generated (see fig.12 loop gain ?). using f p2 and f p3 , perform adjustment with the njw4152 mounted in an actual unit, so as to adequate ly reduce the loop gain in the high frequency region. fig12. loop gain examples f z1 or f z2 f p(lc) f p2 f p3 f z(esr) gain (db) lc gain loop gain compensation gain -40db/dec -20db/dec 0db frequency double pole f p1 * gain increase due to zero technical information njw 41 5 2 - a b application manual
njw4152-ab - 22 - ver.2013-01-23 application characteristics :njw4152gm1-a at v out =5.0v setting (r1=5.1k ? , r2=27k ? , c fb =220pf, r fb =0 ? ) 0 10 20 30 40 50 60 70 80 90 100 1101001000 v in =6v v in =12v v in =18v v in =24v output current i out (ma) efficiency (%) efficiency vs. output current (v out =5.0v, ta=25 o c) f=700khz l=22 h 4.8 4.85 4.9 4.95 5 5.05 5.1 5.15 5.2 1 10 100 1000 output voltage v out (v) output voltage vs. output current (ta=25 o c) output current i out (ma) f=700khz l=22 h v in =6v,12v, 18v, 24v at v out =3.3v setting (r1=5.1k ? , r2=16k ? , c fb =220pf, r fb =0 ? ) 0 10 20 30 40 50 60 70 80 90 100 1101001000 v in =5v v in =12v v in =18v v in =24v output current i out (ma) efficiency (%) efficiency vs. output current (v out =3.3v, ta=25 o c) f=700khz l=22 h 3.24 3.26 3.28 3.3 3.32 3.34 3.36 1 10 100 1000 output voltage v out (v) output voltage vs. output current (ta=25 o c) output current i out (ma) f=700khz l=22 h v in =5v,12v, 18v, 24v at v out =1.5v setting (r1=30k ? , r2=27k ? , c fb =220pf, r fb =10k ? ) 0 10 20 30 40 50 60 70 80 90 100 1101001000 v in =5v v in =12v v in =18v v in =24v output current i out (ma) efficiency (%) efficiency vs. output current (v out =1.5v, ta=25 o c) f=700khz l=22 h 1.44 1.46 1.48 1.5 1.52 1.54 1.56 1 10 100 1000 output voltage v out (v) output voltage vs. output current (ta=25 o c) output current i out (ma) f=700khz l=22 h v in =5v,12v, 18v, 24v technical information njw 41 5 2 -ab application manual
njw4152- a b - 23 - ver.2013-01-23 memo [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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